Pre-emphasis circuit

专利名称：Pre-emphasis circuit

发明人：Takanori Saeki,Yasushi Aoki,Tadashi

Iwasaki,Toshihiro Narisawa,MakotoTanaka,Yoichi Iizuka,Nobuhiro Ooki

申请号：US11493602申请日：20060727公开号：US07345602B2公开日：20080318

专利附图：

摘要：Disclosed is a pre-emphasis circuit including a first parallel-to-serial converter, asecond parallel-to-serial converter, a mixing circuit and a clock generating circuit. The

first parallel-to-serial converter converts parallel data into first serial data, and thesecond parallel-to-serial converter converts the parallel data into second serial data. Themixing circuit receives the first serial data from the first parallel-to-serial converter andthe second serial data from the second parallel-to-serial converter to output a signalemphasizing a change point of the first serial data. The clock generating circuit outputs afirst set of clocks made up of clocks having mutually different phases and a second set ofclocks made up of clocks having mutually different phases to the first and secondparallel-to-serial converters, respectively. The first phase clock of the second set ofclocks corresponds to the second phase clock of the first set of clocks.

申请人：Takanori Saeki,Yasushi Aoki,Tadashi Iwasaki,Toshihiro Narisawa,MakotoTanaka,Yoichi Iizuka,Nobuhiro Ooki

地址：Kanagawa JP,Kanagawa JP,Kanagawa JP,Kanagawa JP,Kanagawa JP,KanagawaJP,Kanagawa JP

国籍：JP,JP,JP,JP,JP,JP,JP

代理机构：Foley & Lardner LLP

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