Architecture of circuitry for generating test mode

专利名称：Architecture of circuitry for generating test

mode signals

发明人：Mickey L. Fandrich,Jerry A. Kreifels,Virgil N.

Kynett

申请号：US07/791772申请日：19911112公开号：US05339320A公开日：19940816

摘要：An arrangement for generating signals for generating a particular set of testconditions within a digital circuit including a plurality of latches for storing individual bitsof data representing individual operations to be accomplished within the digital circuitry,the latches each having input and output terminals; the output terminals of each of thelatches being connected to individual portions of the digital circuitry to effect anindividual operation thereby; apparatus connected to the input terminals of the latchesfor setting individual selected ones of the latches to provide selected test conditions;and apparatus for transferring the condition of a selected number of the latchessimultaneously to effect a selected test condition.

申请人：INTEL CORPORATION

代理机构：Blakely, Sokoloff, Taylor & Zafman

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