LV8415CB-TE-L-H;中文规格书,Datasheet资料

LV8415CB

Overview Functions

Bi-CMOS integrated circuit

Blurring correction driver IC for DSC

H bridge × 2ch driver

LV8415CB is blurring correction driver IC for DSC.

• Hall Amplifier × 2ch

• General-purpose amplifier × 2ch • 8bitDAC for hall bias × 2ch • Three line serial input

• With built-in thermal protection circuit

Specifications

• Actuator driver (saturation drive H bridge) × 2ch • Constant current hall bias circuit × 2ch

• With built-in for PWM signal generation logic circuit × 2ch • 8bitDAC for hall amplifier offset adjustment × 2ch • Two systems in power supply (VM: for actuator, VCC) • With built-in low voltage malfunction prevention circuit

Maximum Ratings at Ta = 25°C

Parameter Symbol Supply voltage 1 Supply voltage 2 Output peak current Output current Hall bias current

Allowable power dissipation Operating temperature Storage temperature

VM max VCC max IO peak IO max IHB max Pd max Topr Tstg

OUT1 to 2 (t ≤ 10msec, duty ≤ 20%) OUT1 to 2

On a specified board *

Conditions Ratings 6660035051

-20 to +85-55 to +150

V V mA mA mA W °C °C

Unit * Specified board: 40.0mm×50.0mm×0.8mm, Four layers fiberglass epoxy circuit board.

Allowable Operating Ratings at Ta = 25°C

Parameter Symbol Supply voltage range 1 Supply voltage range 2 Logic input voltage

VM VCC VIN

Conditions Ratings 2.7 to 5.52.7 to 5.50 to VCC+0.3

V V V

Unit AnyandallSANYOSemiconductorCo.,Ltd.productsdescribedorcontainedhereinare,withregardto\"standardapplication\intendedfortheuseasgeneralelectronicsequipment(homeappliances,AVequipment,communicationdevice,officeequipment,industrialequipmentetc.).Theproductsmentionedhereinshallnotbeintendedforuseforany\"specialapplication\"(medicalequipmentwhosepurposeistosustainlife,aerospaceinstrument,nuclearcontroldevice,burningappliances,transportationmachine,trafficsignalsystem,safetyequipmentetc.)thatshallrequireextremelyhighlevelofreliabilityandcandirectlythreatenhumanlivesincaseoffailureormalfunctionoftheproductormaycauseharmtohumanbodies,norshalltheygrantanyguaranteethereof.Ifyoushouldintendtouseourproductsforapplicationsoutsidethestandardapplicationsofourcustomerwhoisconsideringsuchuseand/oroutsidethescopeofourintendedstandardapplications,pleaseconsultwithuspriortotheintendeduse.Ifthereisnoconsultationorinquirybeforetheintendeduse,ourcustomershallbesolelyresponsiblefortheuse.SpecificationsofanyandallSANYOSemiconductorCo.,Ltd.productsdescribedorcontainedhereinstipulatetheperformance,characteristics,andfunctionsofthedescribedproductsintheindependentstate,andarenotguaranteesoftheperformance,characteristics,andfunctionsofthedescribedproductsasmountedinthecustomer'sproductsorequipment.Toverifysymptomsandstatesthatcannotbeevaluatedinanindependentdevice,thecustomershouldalwaysevaluateandtestdevicesmountedinthecustomer'sproductsorequipment.D2210 SY/82510 SY 20100818-S00003 No.A1787-1/12

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LV8415CB

Electrical Characteristics at Ta = 25°C, VCC = 3.3V, VM = 5.0V

Parameter Symbol Current consumption when standing by

VM current consumption VCC current consumption VCC low voltage cutting voltage Low voltage hysteresis voltage Thermal shutdown temperature Thermal hysteresis width H bridge output (OUT1-2) Output on resistance

Ronu IO = 100mA, Upper-side on resistance Rond IO = 100mA, Under-side on resistance

Output leakage current Diode forward voltage

IO leak VD

ID = -100mA

0.7 0.5 0.7

0.980.71

Ω Ω μA V

IM ICC VTHVCC VTHHYS TSD

VM = 5.0V, ST = ”H”, no load ST = ”H”, no load

Design guarantee

2.110015515

2 2.4 150 175

103.22.6200195

μA mA V mV °C °C

ICCO

ST = ”L”

Conditions

Unit

min typ max

1.0

μA

Ratings

ΔTSD Design guarantee 35 55

Operational amplifier (OP-AMP1-4) Input offset voltage Input offset current Input bias current

Equal phase input voltage range Equal phase signal removal ratio

Large amplitude voltage range Output voltage range

VG

RL = 20kΩ, VIN = 1mV(open loop gain)

1

VCC-0.2

651

10

V/mV

OP_VIO OP_IIO OP_IB VICM

060

±1 ±5 30

±5±50250VCC

mV nA nA V

dB CMR 80 VOH RL = 20kΩ SVR OP_IO

V VOL RL = 20kΩ 0.2V Power supply change removal ratio

Output current (sink/source) Hall bias (HB1-2) Output current

Output saturation voltage Standard voltage Standard voltage Standard voltage load characteristic

Internal CLK frequency for PWM drive CLK frequency

Fclk

13.5

15

17.25

MHz

VREF

1.60IHB VSATHB

RHG = 1kΩ, VHBIN = 1.0V IHB = 1mA

0.95VCC-0.2

1.00

1.05

mA

2

mA

85 dB V 1.65 1.70V VRref IREF = 100μA 1.601.65 1.70V Control pin (ST, SCLK, DATA, STB) Built-in pull-down resistance Input current

Rin

50

100

20

33

2001.050

kΩ μA μA

V V IINL VIN = 0V IINH VIN = 3.3V VINL VINH 2.5

Input “L” level voltage Input “H” level voltage

1.0 No.A1787-2/12

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LV8415CB

Package Dimensions

unit : mm (typ) 3397 TOP VIEW 2.47 SIDE VIEW Pin Assignment

SIDE VIEW0.235BOTTOM VIEW1.2Pd max - TaSpecified circuit board:40.0 × 50.0 × 0.8mm3Four layer glass epoxy boardAllowable power dissipation, Pd max -- W0.40.235A1.00.82.470.4CBD0.60.520.460.69 MAX321FE0.2450.20-300306090120Ambient temperature, Ta -- C0.175SANYO : WLP32(2.47X2.47)FEDCBAOUT1AOUT1BPGNDOUT2AOUT2B(NC_TEST)(NC_TEST) is pin only for the test.Please NC_TESTpin connect GND line.

VMSTSCLKDATASTBVREFVCCVIN+3VIN+4SGNDHB1VIN-3VIN-4HB2Power supply pinGND pinHGND1VOUT3VOUT1VOUT2VOUT4HGND2Output pinLogic control pinVIN+1VIN-1AVIN-1BVIN-2BVIN-2AVIN+2Analog control pin123456Ball side viewNo.A1787-3/12

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LV8415CB

Pin function Pin No. E2 E3 E4 E5 F1 F2 F4 F5 E1 F3 D1 D6 C1 B1 C6 B6 Pin name ST SCLK DATA STB Pin function Input pin. High level 2V to (VCC = 3.3V) Low level 0 to 0.5V (VCC = 3.3V) Equivalent Circuit VCCINGNDOUT1A OUT1B OUT2A OUT2B VM PGND Output pin. (PWM output) VM : POWER – Power supply pin. PGND : POWER – GND pin. VMOTOTPGVCC SGND HB1 HGND1 HB2 HGND2 Signal system power supply pin Signal system GND pin HB1, 2 pin Hall bias source pin HGND1, 2 pin Hall bias current setting pin VCC A1 A2 A3 A6 A5 A4 B3 B4 VIN+1 VIN-1A VIN-1B VIN+2 VIN-2A VIN-2B Hall amplifier input pin VIN+ Hall amplifier+ input pin VIN-A Hall amplifier- input pin VIN-B LPF formation pin (The filter is formed for the noise removal.) INHBHGNDGNDVCCINBIN+INAGNDVOUT1 VOUT2 Hall amplifier output pin. VOUT1 : Hall amplifier 1ch output pin. VOUT2 : Hall amplifier 2ch output pin. VCCOTGNDContinued on next page.

No.A1787-4/12

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LV8415CB

Continued from preceding page.

Pin No. D2 C2 D5 C5 B2 B5 E6 F6 Pin name VIN+3 VIN-3 VIN+4 VIN+4 Pin function General purpose amplifier input pin. VIN+3 : 3ch general purpose amplifier+ input pin VIN-3 : 3ch general purpose amplifier- input pin VIN+4 : 4ch general purpose amplifier+ input pin VIN-4 : 4ch general purpose amplifier- input pin Equivalent Circuit VCCIN+IN-GNDVOUT3 VOUT4 General purpose amplifier output pin. VOUT3 : 3ch general purpose amplifier output pin VOUT4 : 4ch general purpose amplifier output pin VCC OTGNDVREF Internal standard voltage pin VCC/2 output VCCVREFGNDNC-TEST N.C. pin TEST pin Please NC_TEST pin connect GND line. VCCNCGND No.A1787-5/12

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LV8415CB

Block Diagram VCCVMVCC low voltagecutting circuitOverheating protection circuitOUT1AbitPWM10 generation logicOscillationcircuitLogic circuitH bridge circuitOUT1BOUT2ASCLKDATASTBSirial/pararel10 to 12bitPWMgeneration logicLogic circuitH bridge circuitOUT2BPGNDStandard voltage8bit DAC8bit DAC8bit DAC8bit DAC+++++++-HGND1PGNDVREF-VIN+1HB1-HGND2VOUT1VIN-1BVIN-1A-VIN+2HB2-VOUT2VIN-2BVIN-2A-VOUT3VIN-3VIN+3VIN+4-VOUT4VIN-4STHHSetpoint signal(3 line sirial)Hall Out(Yaw)Logic-ChipHall Out(Pitch)No.A1787-6/12

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LV8415CB

3 line serial communication electrical Characteristics at Ta = 25°C, VCC = 3.3V, VM = 5.0V

Parameter Symbol Serial data forwarding pin Logic pin input current

IINL VIN=0V(SCLK, DATA, STB) IINH VIN=3.3V(SCLK, DATA, STB)

Input “H” level voltage Input “L” level voltage

Minimum SCLK “H” pulse width Minimum SCLK “L” pulse width STB regulation time Minimum STB pulse width Data set-up time Data hold time

maximum CLK frequency

VINH SCLK, DATA, STB VINL SCLK, DATA, STB TSCH TSCL Tlat Tlatw Tds Tdh Fclk

0.10.10.10.10.10.12.5

33

1.050

μA V

V μs μs μs μs μs μs μs

4

MHz

Conditions

Unit

min typ max Ratings

1.0

FclkTSCLTSCH

SCLK TdsTdh D10A0A1D11A2DATA

Tlat

STB

Tlatw

Serial data timing condition Serial data input timing chart

ST

D7A0D2D11A1A3D4D10A2D1D3D6D8D0D9D5 DATA

SCLK

STB The latch does the state setting data

It inputs it from A0 in order of D11. The data transfer is done by the rising edge, and after all data transfers, the latch does all data to SCLK by the STB signal standing up. The STB signal accepts and the internal logic of IC doesn't accept the SCLK signal during \"H\".

No.A1787-7/12

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LV8415CB

Serial logic map

PWMh - bridge relation serial map

Input

A0 A1 A2 A3 D0 D1 D2D3 D4 D5 D6D7D8D9D10D110 0 0 0 * * 0 0 0 0 0 0 0 0 0 0 * * 1 0 0 0 0 0 0 0 0 0 * * 0 1 0 0 0 0 0 0 0 0

* * 0 1 1 1 1 1 1 1 1 0 * * 1 1 1 1 1 1 1 1 1 0 Setting mode

Set content 100% 511/512 × 100% 510/512 × 100%

… 2/512 × 100% 1/512 × 100%

0% 1/512 × 100% 2/512 × 100%

… 509/512 × 100% 510/512 × 100% 511/512 × 100%

100% 511/512 × 100% 510/512 × 100%

… 2/512 × 100% 1/512 × 100%

0%

Remarks

Reverse

* * 0 0 0 0 0 0 0 0 0 1 1ch PWM Duty set

* * 1 0 0 0 0 0 0 0 0 * * 0 1 0 0 0 0 0 0 0

* * 1 0 1 1 1 1 1 1 1 * * 0 1 1 1 1 1 1 1 1 * * 1 1 1 1 1 1 1 1 1 1 0 0 0 * * 0 0 0 0 0 0 0 0 0 * * 1 0 0 0 0 0 0 0 0 * * 0 1 0 0 0 0 0 0 0

* * 0 1 1 1 1 1 1 1 1 * * 1 1 1 1 1 1 1 1 1 1 1

1 1 1 0 0 0

0 0 Middle point

Normal rotation

Reverse

* * 0 0 0 0 0 0 0 0 0 1 2ch PWM Duty set

* * 1 0 0 0 0 0 0 0 0 * * 0 1 0 0 0 0 0 0 0

* * 1 0 1 1 1 1 1 1 1 * * 0 1 1 1 1 1 1 1 1 * * 1 1 1 1 1 1 1 1 1 ** 0 1 0 0 0 0 0 0 0 0 0 0 *

** 1 0 0 0 0 0 0 0 *

** 0 1 0 0 0 0 0 0 ****

** 1 0 1 1 1 1 1 1 *

** 0 1 1 1 1 1 1 1 *

** 1 1 1 1 1 1 1 1 *

** 1 1 0 0 0 0 0 0 0 0 0 0 *

** 1 0 0 0 0 0 0 0 **** 0 1 0 0 0 0 0 0 ***

** 1 0 1 1 1 1 1 1 *

** 0 1 1 1 1 1 1 1 *

** 1 1 1 1 1 1 1 1 *

** 0 0 1 0 0 0 0 0 0 0 0 0 *

** 1 0 0 0 0 0 0 0 *

** 0 1 0 0 0 0 0 0 ****

** 1 0 1 1 1 1 1 1 *

** 0 1 1 1 1 1 1 1 *

** 1 1 1 1 1 1 1 1 *

** 1 0 1 0 0 0 0 0 0 0 0 0 *

** 1 0 0 0 0 0 0 0 *

** 0 1 0 0 0 0 0 0 ****

*** 1 0 1 1 1 1 1 1 ** 0 1 1 1 1 1 1 1 *

** 1 1 1 1 1 1 1 1 *The PWMh-bridge driver's ON/OFF operation is done with the ST pin.

1 1

1 1 1 * * * * * * * * * * * * * * * * * * * * * * * * * * * * Middle point

1ch hall bias set (8bit DAC)

2ch hall bias set (8bit DAC)

1ch hall amplifier offset adjustment (8bit DAC)

2ch hall amplifier offset adjustment (8bit DAC)

1/512 × 100% 2/512 × 100%

Normal …

rotation 509/512 × 100%

510/512 × 100% 511/512 × 100%

0V 1/255 × VREF 2/255 × VREF

… 253/255 × VREF 2/255 × VREF

VREF 0V 1/255 × VREF 2/255 × VREF

… 253/255 × VREF 2/255 × VREF

VREF 0V 1/255 × VCC 2/255 × VCC

… 253/255 × VCC 2/255 × VCC

VCC

0V 1/255 × VCC 2/255 × VCC

… 253/255 × VCC 2/255 × VCC

VCC

No.A1787-8/12

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LV8415CB

Hall amplifier gain setting range Hall amplifier relation serial map

Input

Setting mode

A0 A1 A2 A3 D0 D1 D2 D3 0 0 0 1 0 0 0 0 1ch hall amplifier gain setting

1 0 0 0 ( “3” Resistance ÷ “2”

Resistance) 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 2ch hall amplifier gain setting

1 0 0 0 ( “3” Resistance ÷ “2”

Resistance) 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0 1 0 1 0 0 0 0 1ch hall amplifier offset

1 0 0 0 resistance / input resistance 0 1 0 0 ( “1” Resistance ÷ “2”

Resistance) 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 2ch hall amplifier offset

1 0 0 0 resistance / input resistance 0 1 0 0 ( “1” Resistance ÷ “2”

Resistance) 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 Hall amplifier magnification

()Inside: Resistance

10 (36k//3.6k) 20 (72k//3.6k) 40 (144k//3.6k) 50 (180k//3.6k) 60 (216k//3.6k) 70 (252k//3.6k) 90 (324k//3.6k) 100 (360k//3.6k) 110 (396k//3.6k) 120 (432k//3.6K) 140 (504k//3.6k) 150 (0k//3.6k) 160 (570k//3.6k) 170 (612k//3.6k) 190 (684k//3.6k) 200 (720k//3.6k) 10 (36k//3.6k) 20 (72k//3.6k) 40 (144k//3.6k) 50 (180k//3.6k) 60 (216k//3.6k) 70 (252k//3.6k) 90 (324k//3.6k) 100 (360k//3.6k) 110 (396k//3.6k) 120 (432k//3.6K) 140 (504k//3.6k) 150 (0k//3.6k) 160 (570k//3.6k) 170 (612k//3.6k) 190 (684k//3.6k) 200 (720k//3.6k) 10 (36k//3.6k) 20 (72k//3.6k) 40 (144k//3.6k) 50 (180k//3.6k) 60 (216k//3.6k) 70 (252k//3.6k) 90 (324k//3.6k) 100 (360k//3.6k) 110 (396k//3.6k) 120 (432k//3.6K) 140 (504k//3.6k) 150 (0k//3.6k) 160 (570k//3.6k) 170 (612k//3.6k) 190 (684k//3.6k) 200 (720k//3.6k) 10 (36k//3.6k) 20 (72k//3.6k) 40 (144k//3.6k) 50 (180k//3.6k) 60 (216k//3.6k) 70 (252k//3.6k) 90 (324k//3.6k) 100 (360k//3.6k) 110 (396k//3.6k) 120 (432k//3.6K) 140 (504k//3.6k) 150 (0k//3.6k) 160 (570k//3.6k) 170 (612k//3.6k) 190 (684k//3.6k) 200 (720k//3.6k)

No.A1787-9/12

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LV8415CB

General-purpose amplifier ON/OFF setting

Input

Setting mode

A0 A1 A2 A3 D0 D1 0 0 1 1 0 * General-purpose

amplifier 1 1 * * 0 General-purpose

amplifier 2 * 1 Set content Stand-by Operate

Stand-by Operate

Remarks

PWM circuit accuracy setting

Input

Setting mode

A0 A1 A2 A3 D0 D1 1 0 1 1 0 0 0 1 PWM accuracy setting

1 0 * * Set content

Remarks

10bit resolution Initial value 11bit resolution 12bit resolution -

PWM pulse width of moving 1ch (X axis side)

Input [3:0]

Setting mode

A0 A1 A2 A3 D0 D1 D2 D3 0 1 1 1 0 0 0 0 1ch (X axis) side width of

moving 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 Note : 1 pulse = 1CLK

Moving pulse number 0 (Initialization) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

2ch (Y axis side)

Input [7:4]

Setting mode

A0 A1 A2 A3 D4 D5 D6 D7 0 1 1 1 0 0 0 0 2ch (Y axis) side width of

moving 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 Note : 1 pulse = 1CLK

Moving pulse number 0 (Initialization) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

The ON/OFF operation of the hall amplifier and the hall bias is done with the ST pin.

Note : An initial value of A0 to A3 = 1111 is a static test mode. Use it specifying data D0 for one.

TEST mode setting

Input

Setting mode Content Remarks

A0 A1 A2 A3 D0 1 1 1 1 0 External CLK It uses it by the shipment inspection.

NC pin _ TEST mode

1 Internal CLK Internal CLK operation

Note : External CLK mode is for the shipment inspection. Use it with internal CLK.Use it after it internal CLK switches because default is external CLK mode.

No.A1787-10/12

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LV8415CB-TE-L-H