VOLTAGE MIRROR CIRCUIT

申请(专利)号： KR20030091721

专利号： KR20040014380A 主分类号： G05F3/26 申请权利人： ANALOGCHIPS

申请日： 2003-12-16 公开公告日： 2004-02-14

分类号： G05F3/26 发明设计人： SONG, MIN GYU;

SONG, WON CHEOL;

LEE, HAN SU 申请国代码： KR

优先权： 20031216 KR

20030091721

摘 要 附 图：

公开国代码： KR 优先权国家： KR

摘 要：

PURPOSE: A voltage mirror circuit is provided to minimize a voltage error of a final output terminal by forming a current bias circuit, a monitoring resistor, and a terminator within one well.

CONSTITUTION: A current bias circuit(200) includes the first and the second NMOS transistors(N1,N2), the first to the fourth PMOS transistors(P1-P4), and monitoring resistors(R1,R2) in order to apply the driving current to a current driver system(221). An output of an operational amplifier(210) is connected to each gate of the first and the second NMOS transistors(N1,N2). One terminal of the second resistor(R2) is connected to a negative input terminal of the

operational amplifier(210). A bias voltage is applied to a positive input terminal of the operational amplifier(210). 主权项：

전류 구동시스템(221)에 구동전류(IREF)를 미러링하기 위한 전류 바이어스

회로(200)에 있어서 외부에서 인가되는 기준 전압(Vref)을 연산 증폭기(210)의 양의

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