Dual phase-locked loop circuit and method for cont

专利名称：Dual phase-locked loop circuit and method

for controlling the same

发明人：Yong-Wang Liu,Wen-cai Lu,Sterling Smith申请号：US12825438申请日：20100629公开号：US08564340B2公开日：20131022

专利附图：

摘要：A dual phase-locked loop (PLL) circuit includes a phase/frequency detector, acharge pump, a frequency tuning circuit and an N divider. The frequency tuning circuitincludes a coarse-tuning circuit, for coarse-tuning an output frequency of the dual PLL

circuit to approximate a target frequency; a fine-tuning circuit, for fine-tuning the outputfrequency of the dual PLL circuit to the target frequency; and a current control oscillator(CCO), for generating an output signal of the dual PLL circuit. The output frequency ofthe output signal is equal to the target frequency.

申请人：Yong-Wang Liu,Wen-cai Lu,Sterling Smith

地址：Shanghai CN,Shanghai CN,Hsinchu Hsien TW

国籍：CN,CN,TW

代理机构：Edell, Shapiro & Finnan, LLC

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