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18.4 Improving CDR Performance via Estimation

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ISSCC 2006 / SESSION 18 / CLOCKANDDATARECOVERY / 18.418.4Improving CDR Performance via Estimation

Haechang Lee1, Akash Bansal2, Yohan Frans2, Jared Zerbe2, Stefanos Sidiropoulos3, Mark Horowitz1

Stanford University, Stanford, CARambus, Los Altos, CA3

Aeluros, Mountain View, CA

CDR has been proposed for this system [4], the low bandwidthdesired for jitter filtering compromises its ability to track theSSC. Again, these opposing constraints can be decoupled if a CDRcapable of predicting the phase movement due to SSC is built, asshown in Fig. 18.4.4.

A3rd-order estimator can predict the phase of future bits withineach linear section of the triangular profile by estimating thephase, frequency, and frequency-ramp rate of the TX. However, itwill perform worse than a 2nd-order when the frequency-ramprate changes polarity. Thus, the CDR must also estimate whenthe frequency ramp changes sign. There are many ways toextract this information. In the proposed design, the output of thefrequency accumulator (F_acc) is differentiated by subtractingeach sample from the previous one. The sign of this subtractionindicates the polarity of the frequency ramp and draws out asquare wave whose transitions coincide with the switching pointsof the SSC. Unfortunately, since the ramp rate is not large, glitch-es can occur in random locations. Most can be removed by run-ning this pseudo-differentiation at a much slower sample ratesuch that the change in frequency will be larger between sampleswhile others are removed by a filter with hysteresis. AdigitalPLL(DPLL) locked to this output is used to enable one of two fre-quency ramp accumulators (Rp_acc, Rn_acc). In steady state, thissystem operates as a 3rd-order CDR with Rp_acc half of the timeand Rn_acc the other half. The use of a single ramp accumulatorwas investigated, but its ramp rate does not converge as the errorfrom the positive ramp cancels out that from the negative.Saturating the ramp accumulators so that their values stay with-in their expected polarity helps convergence. After tape out, amore robust method of extracting the timing of the modulation isfound. This method compares F_acc with its average to generatea square wave that is 90°offset from the switching points. ADPLLis locked to this signal and its output is digitally phaseshifted by 90°to estimate when to switch the sign of the frequen-cy ramp.

Figure 18.4.6 shows the timing margin of the 2nd-order and thehigher-order CDR as the integral gain is varied when receivingSSC data (BER=10-11). An optimum exists for the 2nd-order estima-tor because of the opposing bandwidth constraints from jitter fil-tering and tracking the SSC. The functionality of the higher-order estimator is verified by checking that its states converge tothe expected values. As expected, the margin of the higher-orderestimator improves at lower gain settings. Unfortunately, due toa very slow beat frequency (several millions of bits, so it was notseen in simulations) generated by the estimation of the switchingpoints, the margin improvement is limited. Simulations showthat removing this bug will result in a timing margin thatincreases monotonically with the reduction in integral gain giv-ing around 0.1UIppoverall margin improvement.

Acknowledgment:

Authors thank MARCO for funding and D. Liu and D. Draper for assis-tance.

References:

[1] S. Sidiropoulos, et al., “ASemidigital Dual Delay-Locked Loop,” IEEEJ. Solid-State Cicuits, Nov., 1997.

[2] H. Lee, et al., “Burst Mode Packet Receiver Using a Second OrderDLL,” Dig. Symp. VLSI Circuits, vol. 32, pp. 1683-1692, June, 2004.

[3] H. Ng, et al., “ASecond-Order Semidigital Clock Recovery CircuitBased on Injection Locking,” IEEE J. Solid-State Circuits, vol. 38, pp.2101-2110, Dec., 2003.

[4] M. Aoyama, et al., “3Gbps, 5000ppm Spread Spectrum SerDes PHYwith Frequency Tracking Phase Interpolator for Serial ATA,” Dig. Symp.VLSI Circuits, June, 2003.

An implementation of the semi-digital dual-loop first-order CDRof [1] is shown in Fig. 18.4.1. The CDR (peripheral) loop consistsof a bang-bang phase detector, gain (pre_filt), binary accumulator(P_acc), and phase DAC. Pre_filt is an accumulator that gener-ates a positive or negative carry when the accumulated errorreaches a certain programmable threshold (±1, 2, 4, or 8) and actsas a linear attenuator (1, 1/2, 1/4, or 1/8). The truncation occur-ring in pre_filt also helps to suppress limit cycles caused by loopdelay [2]. The core loop is both a frequency synthesizer and mul-tiphase generator. The high-frequency jitter tolerance (i.e. timingmargin) of this CDR improves as its bandwidth (loop gain) isreduced since more ISI jitter is removed (Fig. 18.4.5(a)). However,this increases lock time and decreases frequency operation range.Building an estimator that adjusts its loop gain according to oper-ating conditions can remove this tradeoff. Since the first-orderCDR is a phase-domain delta modulator, this estimator is fash-ioned after the adaptive delta modulator (ADM) that adjusts itsloop gain based on the time history of the quantizer output. Amodified adaptation is required due to the loop delay (5 cycles) ofthe CDR. The adaptive block (adapt) accumulates the output ofpre_filt. Every N (e.g. 32) cycles, the absolute value of the accu-mulator (abs_n) is compared to 2 thresholds to decide whether tohalve, double, or keep constant Kp (Fig. 18.4.2). Kpcan changebetween 1, 2, and 4. The option to keep the gain constantimproves the performance by removing unnecessary or incorrectgain changes. The jitter tolerance of this adaptive-gain CDR isequivalent to the first-order CDR with gain of 1 at low frequencyand gain of 1/4 at high frequency (Fig. 18.4.5(b)), thus breakingthe link between high-frequency noise filtering and lock-time/fre-quency-range.

Even if these CDRs are able to operate at a given frequency off-set, their jitter tolerance is degraded as the offset is increased(Fig. 18.4.5(c)). The cause of this degradation is that the wrongestimate for future phase position is being used. With a frequen-cy offset, the future phase is not expected to be constant overtime. A2nd-order estimator that acquires the frequency offset anduses it to predict the timing of future bits corrects this error anddecouples the constraints of jitter filtering and ppm tracking [3].Previous 2nd-order CDRs used pulse/pattern generators at theinput of the phase accumulator to limit the number of steps thephase DAC can make every clock cycle [2,3,4]. By allowing theintegral control to update multiple phase DAC steps, this compo-nent can be removed resulting in the simpler 2nd-order CDR ofFig. 18.4.3. When updating by multiple steps, the phase controlsignals must be retimed close to the phase DAC and aligned tothe timing sample clocks rather than those for data recovery tominimize the impact on BER. As expected, the jitter tolerance ofthis CDR does not degrade significantly with frequency offset(Fig. 18.4.5(d)) regardless of its bandwidth. The slight penaltyseen in Fig. 18.4.5(d) is from the loop driving the error to zeroonly at the slow logic clock cycle such that the residual phase driftcaused by the frequency offset is uncorrected for bits in between. The estimation approach for CDRs can also be applied to systemsthat use a spread spectrum clock (SSC). In SSC, the nominal fre-quency of the TX can vary by 5000ppm in a triangular profilewith a modulation frequency of 30 to 33kHz. While a 2nd-order

• 2006 IEEE International Solid-State Circuits Conference1-4244-0079-1/06 ©2006 IEEEISSCC 2006 / February 7, 2006 / 3:15 PMFigure 18.4.1: First-order semi-digital dual-loop CDR.Figure 18.4.2: First-order CDR with adaptive gain.Figure 18.4.3: Second-order CDR capable of tracking > 5000ppm.100Margin improves by 0.1UIppPre_filt= 1 and 1/41010100Figure 18.4.4: Higher-order CDR for recovering SSC data.0.7First orderw/ max gainAdaptive0.60.5Reducinggain1UIppUIppw/out DJ10.110k100100k1M10M100M0.110k100100k1M10M100MUIpp(a)(b)0.40 and 200ppm10100 and 5000ppm0.30.2UIppUIppIncreasing PPM1Increasing PPM1with DJ0.10.110k(c)100kFrequency (Hz)1M10M100M0.110k(d)100kFrequency (Hz)1M10M100M00.010.020.030.040.050.060.07Integral gainFigure 18.4.5: Jitter tolerance measured according to XAUI specs. Figure 18.4.6: Timing margin (UIpp) as integral gain is varied with SSC data(a) first-order CDR vs. bandwidth, (b) first order with adaptive gain, (BER=10-11) for the second-order (dotted, °) and higher-order (solid,*) (c) first order vs. ppm, and (d) second order vs. ppm.estimators. • 2006 IEEE International Solid-State Circuits Conference1-4244-0079-1/06 ©2006 IEEEISSCC 2006 / SESSION 18 / CLOCKANDDATARECOVERY / 18.4Figure 18.4.1: First-order semi-digital dual-loop CDR.

Margin improves by 0.1UIpp

Pre_filt= 1 and 1/4

100

First orderw/ max gain

Adaptive

Reducinggain

UIppUIpp10.110k100

0.110k100

(a)

100k

10M

100M

(b)

100k

10M

100M

0 and 200ppm

0 and 5000ppm

UIpp1

UIppIncreasing PPMIncreasing PPM

0.110k

(c)

100k

Frequency (Hz)

1M10M100M

0.110k

(d)

100k

Frequency (Hz)

1M10M100M

Figure 18.4.5: Jitter tolerance measured according to XAUI specs. (a) first-order CDR vs. bandwidth, (b) first orderwith adaptive gain, (c) first order vs. ppm, and (d) second order vs. ppm.

w/out DJ

UIpp0.30.2

with DJ

0.1

00.010.020.030.040.050.060.07

Integral gain

Figure 18.4.6: Timing margin (UIpp) as integral gain is varied with SSC data (BER=10-11) for the second-order (dotted, °) and higher-order (solid,*) estimators.

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