Hardware acceleration system for logic simulation

专利名称：Hardware acceleration system for logic

simulation using shift register as local cachewith path for bypassing shift register

发明人：Henry T. Verheyen,William Watt申请号：US112911申请日：20051130

公开号：US20070073999A1公开日：20070329

专利附图：

摘要：A simulation processor includes multiple processor units and an interconnectsystem that communicatively couples the processor units to each other. Each of the

processor units includes a processor element configurable to simulate at least a logicoperation, and a shift register for storing intermediate values generating during the logicsimulation. Each of the processor units further includes one or more multiplexers forselecting one of the entries of the shift register as outputs to be coupled to theinterconnect system. Each of the processor units can also include one or more bypassmultiplexers coupled between the output of the processor element and the interconnectsystem, for providing a path for bypassing the shift register to provide the output of theprocessor element directly to the interconnect system.

申请人：Henry T. Verheyen,William Watt

地址：San Jose CA US,San Jose CA US

国籍：US,US

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