FEATURES
Output frequency range: 300 MHz to 1000 MHz Modulation bandwidth: >500 MHz (3 dB) 1 dB output compression: 11 dBm @ 450 MHz Noise floor: −160 dBm/Hz
Sideband suppression: −41 dBc @ 450 MHz Carrier feedthrough: −50 dBm @ 450 MHz Single supply: 4.75 V to 5.25 V 24-lead LFCSP_VQ package
APPLICATIONS
Cellular communication systems at 450 MHz CDMA2000/GSM
WiMAX/broadband wireless access systems Cable communication equipment Satellite modems
GENERAL DESCRIPTION
The ADL5370 is the first in the fixed-gain quadrature modulator (F-MOD) family designed for use from 300 MHz to 1000 MHz. Its excellent phase accuracy and amplitude balance enable high performance intermediate frequency or direct radio frequency modulation for communication systems.
The ADL5370 provides a greater than 500 MHz, 3 dB baseband bandwidth, making it ideally suited for use in broadband zero IF or low IF-to-RF applications and in broadband digital predistortion transmitters.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
300 MHz to 1000 MHz Quadrature Modulator
ADL5370
FUNCTIONAL BLOCK DIAGRAM
IBBPIBBNLOIPQUADRATUREPHASELOINSPLITTERVOUTQBBN1QBBP00-71160
Figure 1.
The ADL5370 accepts two differential baseband inputs and a single-ended LO and generates a single-ended 50 Ω output. The ADL5370 is fabricated using the Analog Devices, Inc. advanced silicon-germanium bipolar process. It is available in a 24-lead, exposed-paddle, Pb-free, LFCSP_VQ package. Perform-ance is specified over a −40°C to +85°C temperature range. A Pb-free evaluation board is available.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
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TABLE OF CONTENTS
Features..............................................................................................1 Applications.......................................................................................1 Functional Block Diagram..............................................................1 General Description.........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Absolute Maximum Ratings............................................................4 ESD Caution..................................................................................4 Pin Configuration and Function Descriptions.............................5 Theory of Operation......................................................................10 Circuit Description.....................................................................10 Basic Connections..........................................................................11 Optimization...............................................................................12
Applications Information..............................................................13 DAC Modulator Interfacing.....................................................13 Limiting the AC Swing..............................................................13 Filtering........................................................................................13 Using the AD9779 Auxiliary DAC for Carrier Feedthrough Nulling.........................................................................................14 GSM Operation..........................................................................14 LO Generation Using PLLs.......................................................15 Evaluation Board............................................................................16 Characterization Setup..................................................................17 Outline Dimensions.......................................................................19 Ordering Guide..........................................................................19
REVISION HISTORY
10/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
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SPECIFICATIONS
VS = 5 V; TA = 25°C; LO = 0 dBm1 single-ended; baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV dc bias; baseband I/Q frequency (fBB) = 1 MHz, unless otherwise noted. Table 1.
Parameter Conditions in Typ ax Unit ADL5370 LO = 450 MHz Operating Frequency Range Range over which uncompensated sideband suppression < −30 dBc ow frequency 300 MHz High frequency 1000 MHz Output Power VIQ = 1.4 V p-p differential 6.2 dBm Output P1 dB 11 dBm Carrier Feedthrough −50 dBm Sideband Suppression −41 dBc Quadrature Error 0.76 Degrees I/Q Amplitude Balance 0.03 dB Second Harmonic POUT − (fLO + (2 × fBB)), POUT = 6.2 dBm −65 dBc Third Harmonic POUT − (fLO + (3 × fBB)), POUT = 6.2 dBm −54 dBc Output IP2 f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = −2 dBm per tone 60 dBm Output IP3 f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = −2 dBm per tone 24 dBm Noise Floor I/Q inputs = 0 V differential with a 500 mV common-mode bias, −160 dBm/Hz 20 MHz carrier offset
LGSM 6 MHz carrier offset, POUT = 6 dBm, PLO = 6 dBm −157 dBc/Hz LO INPUTS
MM1
LO Drive Level Characterization performed at typical level −7 0 +7 dBm
6 dB Input Return Loss See Figure 9 for a plot of return loss vs. frequency
BASEBAND INPUTS Pin IBBP, Pin IBBN, Pin QBBP, Pin QBBN I and Q Input Bias Level 500 mV
2
Input Bias Current Current sourcing from each baseband input with a bias of 500 mV dc 45 μA Input Offset Current 0.1 μA Differential Input Impedance 2900 kΩ Bandwidth (0.1 dB) LO = 450 MHz, baseband input = 700 mV p-p sine wave on 500 mV dc 70 MHz Bandwidth (1 dB) LO = 450 MHz, baseband input = 700 mV p-p sine wave on 500 mV dc 350 MHz POWER SUPPLIES Pin VPS1 and Pin VPS2 Voltage 4.75 5.25 V Supply Current 205 mA
12
High LO drive reduces noise at a 6 MHz carrier offset in GSM applications.
See V-to-I converter discussion in the Circuit Description section for architecture information.
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ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
Parameter Rating may cause permanent damage to the device. This is a stress Supply Voltage VPOS 5.5 V rating only; functional operation of the device at these or any IBBP, IBBN, QBBP, QBBN 0 V to 2 V other conditions above those indicated in the operational LOIP and LOIN 13 dBm section of this specification is not implied. Exposure to absolute Internal Power Dissipation 1375 mW maximum rating conditions for extended periods may affect θJA (Exposed Paddle Soldered Down) 54°C/W device reliability.
Maximum Junction Temperature Operating Temperature Range Storage Temperature Range
159°C
−40°C to +85°C −65°C to +150°C
ESD CAUTION
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
QBBPQBBNCOM4COM4IBBNIBBPCOM1COM1VPS1VPS1VPS1VPS1242322212019123456ADL5370TOP VIEW(Not to Scale)181716151413VPS5VPS4VPS3VPS2VPS2VOUTCOM27LOIP8LOIN9COM210COM311COM31206117-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1, 2, 7, 10 to 12, 21, 22
3 to 6, 14 to 18
Mnemonic COM1, COM2, COM3, COM4 VPS1, VPS2, VPS3, VPS4, VPS5 IBBP, IBBN, QBBN, QBBP
Description
Input Common Pins. Connect to ground plane via a low impedance path.
Positive Supply Voltage Pins. All pins should be connected to the same supply (VS). To ensure adequate external bypassing, connect 0.1 μF capacitors between each pin and ground. Adjacent power supply pins of the same name can share one capacitor (see Figure 25).
Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs must be dc-biased to 500 mV dc, and must be driven from a low impedance source. Nominal characterized ac signal swing is 700 mV p-p on each pin. This results in a differential drive of 1.4 V p-p with a 500 mV dc bias. These inputs are not self-biased and must be externally biased.
50 Ω Single-Ended Local Oscillator Input. Internally dc-biased. Pins must be ac-coupled. AC-couple LOIN to ground and drive LO through LOIP.
Device Output. Single-ended, 50 Ω internally biased RF output. Pin must be ac-coupled to the load. Connect to ground plane via a low impedance path.
19, 20, 23, 24
8, 9 13
LOIP, LOIN VOUT
Exposed Paddle
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TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V; TA = 25°C; LO = 0 dBm single-ended; baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV dc bias; baseband I/Q frequency (fBB) = 1 MHz, unless otherwise noted.
871412TA = –40°CTA = +25°CTA = –40°CSSB OUTPUT POWER (dBm)65432TA = +85°COUTPUT P1dB (dBm)1086420250TA = +25°CTA = +85°C06117-0030250450650850105012501450450650850105012501450LO FREQUENCY (MHz)
Figure 3. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (fLO)
and Temperature
87
SSB OUTPUT POWER (dBm)654
VS = 4.75V32
06117-004
Figure 6. SSB Output 1 dB Compression Point (OP1dB) vs. fLO and Temperature
LO FREQUENCY (MHz)1412VS = 5.25VVS = 5VOUTPUT P1dB (dBm)VS = 5.25V1086420250VS = 5VVS = 4.75V0250450650850105012501450450650850105012501450LO FREQUENCY (MHz)
LO FREQUENCY (MHz)06117-0071
06117-0061
Figure 4. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (fLO)
and Supply
5Figure 7. SSB Output 1 dB Compression Point (OP1dB) vs. fLO and Supply
9012060OUTPUT POWER VARIANCE (dB)1501450MHzS22 OF OUTPUT1450MHz180250MHzS11 OF LOIP21006117-0353000
330250MHz240300270–5BASEBAND FREQUENCY (MHz)
06117-0081101001000
Figure 5. I and Q Input Bandwidth Normalized to Gain @ 1 MHz
(fLO = 500 MHz)
Rev. 0 | Page 6 of 20
Figure 8. Smith Chart of LOIP S11 and VOUT S22 .
(fLO from 250 MHz to 1450 MHz)
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00–10SIDEBAND SUPPRESSION (dBc)–5RETURN LOSS (dB)–20–30TA = +85°CTA = –40°C–40–50–60–70TA = +25°C06117-012–10–15–2006117-009–80–90250–25250450650850105012501450450650850105012501450LO FREQUENCY (MHz)LO FREQUENCY (MHz)
Figure 12. Sideband Suppression vs. fLO and Temperature
Multiple Devices Shown
0–10SIDEBAND SUPPRESSION (dBc)
Figure 9. Return Loss (S11) of LOIP
0–10CARRIER FEEDTHROUGH (dBm)–20–30–40–50–60–7006117-010–20–30–40–50–60–70TA = +25°C4506508501050125006117-013TA = –40°CTA = +85°C–80–90250–80–902504506508501050125014501450LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 10. Carrier Feedthrough vs. fLO and Temperature
Multiple Devices Shown
0
Figure 13. Sideband Suppression vs. fLO and Temperature after Nulling at 25°C
Multiple Devices Shown
–20
SECOND ORDER DISTORTION, THIRD ORDERDISTORTION, CARRIER FEEDTHROUGH,SIDEBAND SUPPRESSIONSSB OUTPUT POWER15–10CARRIER FEEDTHROUGH (dBm)–30
THIRD ORDER (dBc)10SSB OUTPUT POWER (dBm)06117-014–20–30–40–50–60–70
06117-011–40
CARRIERFEEDTHROUGH(dBm)5–50
SIDEBANDSUPPRESSION (dBc)0–60–5–70
SECOND ORDER (dBc)–10–80–90250
450650850105012501450
–800.2
0.61.01.41.82.22.63.0
–153.4
LO FREQUENCY (MHz)
BASEBAND INPUT VOLTAGE (V p-p)
Figure 11. Carrier Feedthrough vs. fLO and Temperature after Nulling at 25°C
Multiple Devices Shown
Figure 14. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level
(fLO = 450 MHz)
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–201530SECOND ORDER DISTORTION, THIRD ORDERDISTORTION, CARRIER FEEDTHROUGH,SIDEBAND SUPPRESSIONOUTPUT THIRD ORDER INTERCEPT (dBm)THIRD ORDER (dBc)–30SSB OUTPUT POWER–40CARRIERFEEDTHROUGH(dBm)10TA = –40°C25SSB OUTPUT POWER (dBm)520TA = +25°CTA = +85°C–50SIDEBANDSUPPRESSION (dBc)015–60SECOND ORDER (dBc)–510–70–1006117-015506117-023–800.20.61.01.41.82.22.63.0–153.40250450650850105012501450BASEBAND INPUT VOLTAGE (V p-p)
LO FREQUENCY (MHz)
Figure 15. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level
(fLO = 900 MHz)
SECOND AND THIRD ORDER DISTORTION (dBc)Figure 18. OIP3 vs. Frequency and Temperature
–20OUTPUT SECOND ORDER INTERCEPT (dBm)70TA = –40°C6050403020100250TA = +25°CTA = +85°C–30–40THIRDORDER = +25°C–50THIRDORDER = +85°CTHIRDORDER = –40°CSECOND ORDER = –40°C–60–70SECOND ORDER = +25°C–802504506508501050125006117-0161450450650850105012501450
Figure 16. Second- and Third-Order Distortion vs. fLO and Temperature
(Baseband I/Q Amplitude = 1.4 V p-p differential)
–20SECOND ORDER DISTORTION, THIRD ORDERDISTORTION, CARRIER FEEDTHROUGH,SIDEBAND SUPPRESSIONLO FREQUENCY (Hz)LO FREQUENCY (MHz)06117-024SECOND ORDER = +85°C
Figure 19. OIP2 vs. Frequency and Temperature
–20SECOND ORDER DISTORTION, THIRD ORDERDISTORTION, CARRIER FEEDTHROUGH,SIDEBAND SUPPRESSION7SSB OUTPUT POWER6SSB OUTPUT POWER (dBm)15105CARRIERFEEDTHROUGH (dBm)THIRD ORDER (dBc)0–5–10–15–2006117-018–30–40–50–60–70SECOND ORDER (dBc)–80–90–30–40–50–60–70–80SIDEBAND SUPPRESSION (dBc)CARRIER FEEDTHROUGH (dBm)THIRD ORDER (dBc)543210100SECOND ORDER (dBc)06117-034110BASEBAND FREQUENCY (Hz)–90–7–5–3–11357
LO AMPLITUDE (dBm)SSB OUTPUT POWER (dBm)SIDEBANDSUPPRESSION (dBc)SSB OUTPUT POWER
Figure 17. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. fBB and Temperature (fLO = 450 MHz) Figure 20. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. LO Amplitude (fLO = 450 MHz)
Rev. 0 | Page 8 of 20
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16FLO = 450MHz–2015101412SECOND ORDER DISTORTION, THIRD ORDERDISTORTION, CARRIER FEEDTHROUGH,SIDEBAND SUPPRESSION–30SSB OUTPUT POWER–40–50–60–70–80–90–7CARRIER FEEDTHROUGH (dBm)SSB OUTPUT POWER (dBm)50QUANTITY1086420THIRD ORDER (dBc)SIDEBAND SUPPRESSION (dBc)SECOND ORDER (dBc)–5–10–15–2006117-019–161.4–161.2–161.0–160.8–160.6–160.4–160.2–160.0–159.8–159.6–159.4–159.2–159.0–158.8–5–3–11357NOISE (dBm/Hz) AT 20MHz OFFSET–158.606117-036LO AMPLITUDE (dBm)
Figure 23. 20 MHz Offset Noise Floor Distribution at fLO = 450 MHz
(I/Q Amplitude = 0 mV p-p with 500 mV dc bias)
Figure 21. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. LO Amplitude (fLO = 900 MHz)
0.230.22VS = 5.25V0.210.200.190.180.1706117-020
SUPPLY CURRENT (A)VS = 5VVS = 4.75V0.160.15–4025TEMPERATURE (°C)85
Figure 22. Power Supply Current vs. Temperature
Rev. 0 | Page 9 of 20
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THEORY OF OPERATION
CIRCUIT DESCRIPTION
Overview
The ADL5370 can be divided into five circuit blocks: the local oscillator (LO) interface, the baseband voltage-to-current(V-to-I) converter, the mixers, the differential-to-single-ended (D-to-S) amplifier, and the bias circuit. A detailed block diagram of the device is shown in Figure 24.
LOIPLOINPHASESPLITTERV-to-I Converter
The differential baseband inputs (QBBP, QBBN, IBBN, IBBP) consist of the bases of PNP transistors, which present a high impedance. The voltages applied to these pins drive the V-to-I stage that converts baseband voltages into currents. The differential output currents of the V-to-I stages feed each of their respective Gilbert-cell mixers. The dc common-mode voltage at the baseband inputs sets the currents in the two mixer cores. Varying the
baseband common-mode voltage varies the current in the mixer and affects overall modulator performance. The recommended dc voltage for the baseband common-mode voltage is 500 mV dc.
Mixers
IBBPIBBNΣQBBPQBBNOUT06117-032
Figure 24. Block Diagram
The ADL5370 has two double-balanced mixers: one for the in-phase channel (I channel) and one for the quadrature channel (Q channel). Both mixers are based on the Gilbert-cell design of four cross-connected transistors. The output currents from the two mixers sum together into a load. The signal developed across this load is used to drive the D-to-S amplifier.
The LO interface generates two LO signals in quadrature. These signals are used to drive the mixers. The I and Q baseband input signals are converted to currents by the V-to-I stages, which then drive the two mixers. The outputs of these mixers combine to feed the differential-to-single-ended amplifier, which provides a 50 Ω output interface. The bias cell generates
reference currents for the V-to-I stage and the D-to-S amplifier.
D-to-S Amplifier
The output D-to-S amplifier consists of a totem pole output stage. The 50 Ω output impedance is established by an on-chip resistor. The D-to-S output is internally dc-biased and should be ac-coupled at its output (VOUT).
Bias Circuit
An on-chip band gap reference circuit is used to generate a proportional-to-absolute temperature (PTAT) reference current for the V-to-I stage and a temperature independent current for the D-to-S output stage.
LO Interface
The LO interface consists of a polyphase quadrature splitter followed by a limiting amplifier. The LO input impedance is set by the polyphase. The LO can be driven either single-ended or differentially. When driven single-ended, the LOIN pin should be ac-grounded via a capacitor. Each quadrature LO signal then passes through a limiting amplifier that provides the mixer with a limited drive signal.
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BASIC CONNECTIONS
Figure 25 shows the basic connections for the ADL5370.
QBBPQBBNIBBNIBBPBaseband Inputs
The baseband inputs QBBP, QBBN, IBBP, and IBBN must be driven from a differential source. The nominal drive level of 1.4 V p-p differential (700 mV p-p on each pin) should be biased to a common-mode level of 500 mV dc.
The dc common-mode bias level for the baseband inputs may range from 400 mV to 600 mV. This results in a reduction in the usable input ac swing range. The nominal dc bias of 500 mV allows for the largest ac swing, limited on the bottom end by the ADL5370 input range and on the top end by the output compliance range on most digital-to-analog converters (DAC) from Analog Devices.
QBBNCOM4COM4QBBPIBBN242322212019IBBPC160.1µFC150.1µFCOM1COM1VPS1VPOS12345618VPS5VPS4VPS3VPS2C130.1µFC140.1µFVPOSC11OPENVOUT06117-033Z1ADL5370171615LO Input
A single-ended LO signal should be applied to the LOIP pin through an ac-coupling capacitor. The recommended LO drive power is 0 dBm. The LO return pin, LOIN, should be ac-coupled to ground through a low impedance path.
The nominal LO drive of 0 dBm can be increased to up to 7 dBm to realize an improvement in the noise performance of the modulator. This improvement is tempered by degradation in the sideband suppression performance (see Figure 20) and, therefore, should be used judiciously. If the LO source cannot provide the 0 dBm level, then operation at a reduced power below 0 dBm is acceptable. Reduced LO drive results in slightly increased modulator noise. The effect of LO power on sideband suppression and carrier feedthrough is shown in Figure 20. The effect of LO power on GSM noise is shown in Figure 35.
VPS1VPS1VPS1C120.1µFEXPOSED PADDLEVPS214VOUT13COUT100pF10LOIPCOM2LOINCOM2COM3GNDCLOP100pFLOCLON100pFCOM31211789 Figure 25. Basic Connections for the ADL5370
Power Supply and Grounding
All the VPS pins must be connected to the same 5 V source.
Adjacent pins of the same name can be tied together and decoupled with a 0.1 μF capacitor. These capacitors should be located as close as possible to the device. The power supply can range between 4.75 V and 5.25 V.
The COM1 pin, COM2 pin, COM3 pin, and COM4 pin should be tied to the same ground plane through low impedance paths. The exposed paddle on the underside of the package should also be soldered to a low thermal and electrical impedance ground plane. If the ground plane spans multiple layers on the circuit board, they should be stitched together with nine vias under the exposed paddle. The Analog Devices AN-772 application note discusses the thermal and electrical grounding of the LFCSP_VQ in greater detail.
RF Output
The RF output is available at the VOUT pin (Pin 13). This pin must also be ac-coupled. The VOUT pin has a nominal broadband impedance of 50 Ω and does not need further external matching.
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OPTIMIZATION
The carrier feedthrough and sideband suppression performance of the ADL5370 can be improved through the use of optimiza-tion techniques.
It is often desirable to perform a one-time carrier null calibra-tion. This is usually performed at a single frequency. Figure 27 shows how carrier feedthrough varies with LO frequency over a range of ±50 MHz on either side of a null at 450 MHz.
–25–30CARRIER FEEDTHROUGH (dBm)Carrier Feedthrough Nulling
Carrier feedthrough results from minute dc offsets that occur between each of the differential baseband inputs. In an ideal modulator the quantities (VIOPP − VIOPN) and (VQOPP − VQOPN) are equal to zero, and this results in no carrier feedthrough. In a real modulator, those two quantities are nonzero; and, when mixed with the LO, they result in a finite amount of carrier feedthrough. The ADL5370 is designed to provide a minimal amount of carrier feedthrough. Should even lower carrier feedthrough levels be required, minor adjustments can be made to the (VIOPP − VIOPN) and (VQOPP − VQOPN) offsets. The I-channel offset is held constant while the Q-channel offset is varied, until a minimum carrier feedthrough level is obtained. The Q-channel offset required to achieve this minimum is held constant while the offset on the I-channel is adjusted, until a new minimum is reached. Through two iterations of this process, the carrier feedthrough can be reduced to as low as the output noise. The ability to null is sometimes limited by the resolution of the offset adjustment. Figure 26 shows the relationship of carrier feedthrough vs. dc offset as null.
–60–64CARRIER FEEDTHROUGH (dBm)–35–40–45–50–55–60–65–70–75–80–8540041042043044045046047048049006117-028500
Figure 27. Carrier Feedthrough vs. Frequency After Nulling at 450 MHz
LO FREQUENCY (MHz)Sideband Suppression Optimization
Sideband suppression results from relative gain and relative phase offsets between the I and Q channels and can be suppressed through adjustments to those two parameters.
Figure 28 illustrates how sideband suppression is affected by the gain and phase imbalances.
0–10SIDEBAND SUPPRESSION (dBc)–68–72–76–80–84–88–300–240–180–1202.5dB–201.25dB–300.5dB0.25dB–400.125dB–500.05dB0.025dB–600.0125dB–700dB06117-02606117-027–80–900.01–60060120180240300VP –VN OFFSET (µV)
0.11PHASE ERROR (Degrees)10100Figure 26. Carrier Feedthrough vs. DC Offset Voltage at 450 MHz
Note that throughout the nulling process, the dc bias for the baseband inputs remains at 500 mV. When no offset is applied
VIOPP = VIOPN = 500 mV, or VIOPP − VIOPN = VIOS = 0 V
When an offset of +VIOS is applied to the I-channel inputs
VIOPP = 500 mV + VIOS/2, and
VIOPN = 500 mV − VIOS/2, such that VIOPP − VIOPN = VIOS
The same applies to the Q channel.
Figure 28. Sideband Suppression vs. Quadrature Phase Error for Various
Quadrature Amplitude Offsets
Figure 28 underlines the fact that adjusting only one parameter improves the sideband suppression only to a point, unless the other parameter is also adjusted. For example, if the amplitude offset is 0.25 dB, improving the phase imbalance better than 1° does not yield any improvement in the sideband suppression. For optimum sideband suppression, an iterative adjustment between phase and amplitude is required.
The sideband suppression nulling can be performed either through adjusting the gain for each channel or through the modification of the phase and gain of the digital data coming from the digital signal processor.
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APPLICATIONS INFORMATION
DAC MODULATOR INTERFACING
The ADL5370 is designed to interface with minimal components to members of the Analog Devices family of DACs. These DACs feature an output current swing from 0 to 20 mA, and the interface described in this section can be used with any DAC that has a similar output.
AD9779OUT1_P93RBIP50Ω92OUT1_NRBIN50ΩRSLI100Ω20IBBN19ADL5370IBBPDriving the ADL5370 with an Analog Devices TxDAC®
An example of the interface using the AD9779 TxDAC is shown in Figure 31. The baseband inputs of the ADL5370 require a dc bias of 500 mV. The average output current on each of the outputs of the AD9779 is 10 mA. Therefore, a single 50 Ω resistor to ground from each of the DAC outputs results in an average current of 10 mA flowing through each of the resistors, thus producing the desired 500 mV dc bias for the inputs to the ADL5370.
AD9779OUT1_P93RBIP50Ω92OUT1_NRBIN50Ω2019OUT2_N84RBQN50ΩRBQP50Ω8323QBBNRSLQ100ΩQBBP06117-030OUT2_P24
Figure 30. AC Voltage Swing Reduction Through the Introduction
of a Shunt Resistor Between Differential Pair
ADL5370IBBPThe value of this ac voltage swing limiting resistor is chosen based on the desired ac voltage swing. Figure 31 shows the relationship between the swing-limiting resistor and the peak-to-peak ac swing that it produces when 50 Ω bias-setting resistors are used.
2.01.8IBBNDIFFERENTIAL SWING (V p-p)1.61.41.21.00.80.60.40.2010100RL (Ω)100006117-025OUT2_N84RBQN50ΩRBQP50Ω8323QBBNOUT2_PQBBP
Figure 29. Interface Between the AD9779 and ADL5370 with 50 Ω Resistors to Ground to Establish the 500 mV DC Bias for the ADL5370 Baseband Inputs
The AD9779 output currents have a swing that ranges from 0 mA to 20 mA. With the 50 Ω resistors in place, the ac voltage swing going into the ADL5370 baseband inputs ranges from 0 V to 1 V. A full-scale sine wave out of the AD9779 can be described as a 1 V p-p single-ended (or 2 V p-p differential) sine wave with a 500 mV dc bias.
06117-0292410000
Figure 31. Relationship Between the AC Swing-Limiting Resistor and the
Peak-to-Peak Voltage Swing with 50 Ω Bias-Setting Resistors
FILTERING
It is necessary to low-pass filter the DAC outputs to remove images when driving a modulator. The interface for setting up the biasing and ac swing that was discussed in the Limiting the AC Swing section lends itself well to the introduction of such a filter. The filter can be inserted between the dc bias setting
resistors and the ac swing-limiting resistor. Doing so establishes the input and output impedances for the filter.
An example is shown in Figure 32 with a third-order elliptical filter with a 3 dB frequency of 3 MHz. Matching input and output impedances makes the filter design easier, so the shunt resistor chosen is 100 Ω, producing an ac swing of 1 V p-p differential.
LIMITING THE AC SWING
There are situations in which it is desirable to reduce the ac voltage swing for a given DAC output current. This can be achieved through the addition of another resistor to the interface. This resistor is placed in shunt between each side of the differential pair, as shown in Figure 30. It has the effect of reducing the ac swing without changing the dc bias already established by the 50 Ω resistors.
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AD9779OUT1_P93RBIP50Ω92OUT1_NRBIN50Ω1.1nFC1ILPI2.7nHADL537019RSLI100Ω20IBBNIBBPGSM OPERATION
Figure 34 shows the GSM EVM and spectral mask performance vs. output power for the ADL5370 at 450 MHz. For a given LO amplitude, the performance is independent of output power.
–35250kHzEVMRMS (%)2.0–42–49–56–63–70–77–84–911200kHz600kHz400kHz0.51.1nFC2ILNI2.7nHLNQ2.7nHOUT2_NQBBNRBQN50ΩRBQP8350Ω1.1nFC1Q1.1nFC2QRSLQ100ΩQBBP06117-031EVMPK (%)1.0OUT2_P24LPQ2.7nH
Figure 32. DAC Modulator Interface with 3 MHz Third-Order Low-Pass Filter
USING THE AD9779 AUXILIARY DAC FOR CARRIER FEEDTHROUGH NULLING
The AD9779 features an auxiliary DAC that can be used to inject small currents into the differential outputs for each main DAC channel. This feature can be used to produce the small offset voltages necessary to null out the carrier feedthrough from the modulator. Figure 33 shows the interface required to utilize the auxiliary DACs. This adds four resistors to the interface.
90AUX1_P01234567OUTPUT POWER (dBm)06117-0390RMS AND PEAK EVM (%)8423 250kHz, 400kHz, 600kHz, AND 1200kHzSPECTRAL MASK (dBc/30KHz)1.5
Figure 34. GSM EVM and Spectral Performance vs. Channel Power at
450 MHz vs. Output Power; LO Power = 0 dBm
Figure 35 shows the GSM EVM, spectral mask performance and 6 MHz offset noise vs. LO amplitude at 450 MHz with an output power of 6 dBm. Increasing the LO drive level improves the noise performance but degrades EVM performance.
–353.12.9250kHzEVMPK (%)AD9779OUT1_P500Ω93RBIP50ΩRBIN9250Ω250Ω19RSLI100Ω206MHzNOISE(dBc/100kHz)250kHz,400kHz,600kHzAND1200kHzSPECTRALMASK(dBc/30kHz)LPI2.7nH1.1nFC2ILNI2.7nHADL5370IBBP–42–49–56–63–70–77–84–91–98EVMRMS (%)600kHz400kHz2.72.52.32.11.91.71.51200kHz1.1nFC1IOUT1_N250ΩAUX1_N89500Ω87AUX2_N500ΩOUT2_N84RBQN50ΩRBQP8350Ω1.1nFC1Q250ΩIBBN1.31.1LNQ2.7nH23–105QBBN1.1nFC2Q–4–20246RSLQ100Ω24QBBP06117-041LO AMPLITUDE (dBm)06117-040–112–66 MHz OFFSET NOISE0.9RMS AND PEAK EVM (%)
OUT2_PAUX2_P86500Ω250ΩLPQ2.7nHFigure 35. GSM EVM, Spectral Performance, and 6 MHz Noise Floor vs.
LO Power at 450 MHz; Output Power = 6 dBm
Figure 33. DAC Modulator Interface with Auxiliary DAC Resistors
Figure 35 illustrates that an LO amplitude of 0 dBm provides the ideal operating point for noise and EVM for a GSM signal at 450 MHz.
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LO GENERATION USING PLLS
Analog Devices has a line of PLLs that can be used for
generating the LO signal. Table 4 lists the PLLs together with their maximum frequency and phase noise performance. Table 4. ADI PLL Selection Table
Phase Noise @ 1 kHz Offset
Part Frequency FIN (MHz) and 200 kHz PFD (dBc/Hz) ADF4110 550 −91 @ 540 MHz ADF4111 1200 −87@ 900 MHz ADF4112 3000 −90 @ 900 MHz ADF4113 4000 −91 @ 900 MHz ADF4116 550 −89 @ 540 MHz ADF4117 1200 −87 @ 900 MHz ADF4118 3000 −90 @ 900 MHz
TRANSMIT DAC OPTIONS
The AD9779 recommended in the previous sections of this data
sheet is by no means the only DAC that can be used to drive the ADL5370. There are other appropriate DACs, depending on the level of performance required. Table 6 lists the dual Tx-DACs offered by Analog Devices.
Table 6. Analog Devices Dual Tx—DAC Selection Table
Part Resolution (Bits)
MAD9709 8 AD9761 10 AD9763 10 AD9765 12 AD9767 14 AD9773 12 AD9775 14 AD9777 16 AD9776 12 AD9778 14 AD9779 16 Update Rate (MSPS Min) 125 40 125 125 125 160 160 160 1000 1000 1000
The ADF4360 comes as a family of chips, with nine operating frequency ranges. One is chosen, depending on the local oscillator frequency required. While the use of the integrated synthesizer may come at the expense of slightly degraded noise performance from the ADL5370, it can be a cheaper alternative to a separate PLL and VCO solution. Table 5 shows the options available.
Table 5. ADF4360 Family Operating Frequencies
Part
ADF4360-0 ADF4360-1 ADF4360-2 ADF4360-3 ADF4360-4 ADF4360-5 ADF4360-6 ADF4360-7 ADF4360-8
Output Frequency Range (MHz) 2400 to 2725 2050 to 2450 1850 to 2150 1600 to 1950 1450 to 1750 1200 to 1400 1050 to 1250 350 to 1800 65 to 400
All DACs listed have nominal bias levels of 0.5 V and use the same simple DAC-modulator interface that is shown in Figure 31.
MODULATOR/DEMODULATOR OPTIONS
Table 7 lists other Analog Devices modulators and demodulators. Table 7. Modulator/Demodulator Options
Frequency Range (MHz) Part od/Demod AD8345 Mod 140 to 1000 AD8346 Mod 800 to 2500 AD8349 Mod 700 to 2700 ADL5390 Mod 20 to 2400 ADL5385 Mod 50 to 2200 ADL5371 Mod 700 to 1300 ADL5372 Mod 1600 to 2400 ADL5373 Mod 2300 to 3000 ADL5374 Mod 3000 to 4000 AD8347 Demod 800 to 2700 AD8348 Demod 50 to 1000 AD8340 Vector mod 700 to 1000 AD8341 Vector mod 1500 to 2400
Comments
External quadrature
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EVALUATION BOARD
Populated RoHS-compliant evaluation boards are available for evaluation of the ADL5370. The ADL5370 package has an exposed paddle on the underside. This exposed paddle must be soldered to the board (see the Power Supply and Grounding discussion in the Basic Connections section). The evaluation board is designed without any components on the underside so heat can be applied to the underside for easy removal and replacement of the ADL5370.
QBBPQBBNIBBNIBBPRFPQRFNQCFNQCFNI0Ω0ΩOPENOPENRTQCFPQOPENOPENRFNI0ΩRTIOPENRFPI0ΩCFPIOPENC160.1µFL120ΩC150.1µFL110ΩQBBNCOM4COM4QBBPIBBNIBBP Figure 37. Evaluation Board Layout, Top Layer.
06117-022242322212019 COM1COM1VPS1VPS1VPS1VPS1C120.1µF12345618VPS5VPS4VPS3VPS2VPS2VOUTCOUT100pFC130.1µFVPOS1514EXPOSED PADDLE13C11OPENVOUT06117-02110COM2LOINLOIPCOM2COM3GNDCLOP100pFLOCLON100pFCOM31211789VPOSZ1ADL53701716C140.1µF
Figure 36. ADL5370 Evaluation Board Schematic
Table 8. Evaluation Board Configuration Options
Component Description VPOS, GND Power Supply and Ground Clip Leads. RFPI, RFNI, RFPQ, RFNQ, CFPI, Baseband Input Filters. These components can be used CFNI, CFPQ, CFNQ, RTQ, RTI to implement a low-pass filter for the baseband signals.
See the Filtering discussion in the Applications Information section.
Default Condition Not applicable
RFNQ, RFPQ, RFNI, RFPI = 0 Ω (0402) CFNQ, CFPQ, CFNI, CFPI = Open (0402) RTQ, RTI = Open (0402)
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CHARACTERIZATION SETUP
AEROFLEX IFR 3416250kHz TO 6GHz SIGNAL GENERATORFREQ 4MHz LEVEL 0dBmBIAS 0.5VGAIN 0.7VBIAS 0.5VGAIN 0.7VRFOUTR AND S SPECTRUM ANALYZERFSU 20Hz TO 8GHzLOCONNECT TO BACK OF UNITI OUTI/AMQ OUTQ/FM90°AGILENT 34401AMULTIMETER0.175 ADCIPVPOS +5VAGILENT E3631APOWER SUPPLYINQPOUTQNVPOSGNDFMODLOIQ0°+6dBmRFINFMOD TEST SETUPOUTPUT5.0000.175A06117-037+6V–+COM–±25V
Figure 38. Characterization Bench Setup
The primary setup used to characterize the ADL5370 is shown in Figure 38. This setup was used to evaluate the product as a single-sideband modulator. The Aeroflex signal generator supplied the local oscillator (LO) and differential I and Q baseband
signals to the device under test, DUT. The typical LO drive was 0 dBm. The I channel is driven by a sine wave, and the Q channel is driven by a cosine wave. The lower sideband is the single sideband (SSB) output.
The majority of characterization for the ADL5370 was performed using a 1 MHz sine wave signal with a 500 mV common-mode voltage applied to the baseband signals of the DUT. The baseband signal path was calibrated to ensure that the VIOS1 and VQOS offsets on the baseband inputs were minimized, as close as possible, to 0 V before connecting to the DUT.
1
See the Carrier Feedthrough Nulling section for the definitions of VIOS
and VQOS.
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TEKTRONIX AFG3252DUAL FUNCTIONARBITRARY FUNCTION GENERATORR AND S SMT 06SIGNAL GENERATORCH1 OUTPUTCH11MHzAMPL700mVp-pPHASE 0°CH21MHzAMPL700mVp-pPHASE90°0°AGILENT E3631APOWER SUPPLYCH2 OUTPUTFREQ 4MHz TO 4GHzLEVEL 0dBmRFOUTIQ90°SINGLE TO DIFFERENTIALCIRCUIT BOARDLOFMOD TEST RACK5.0000.350AQ IN ACFMODCHAR BDGNDIPIPINQPOUTOUTPUTLOVPOS +5V+–6V+±25VCOM–Q IN DCCMTSENVPOSBVPOSAINAGNDIN1IN1VP1QPQN+5VVPOS +5VAGILENT E3631APOWER SUPPLY–5VVN1I IN DCCMI IN ACQNGNDVPOSR AND S FSEA 30SPECTRUM ANALYZER0.5000.010ARFIN100MHz TO 4GHz+6dBmVCM = 0.5V+6V–+±25VCOM–AGILENT 34401AMULTIMETER0.200 ADC06117-038 Figure 39. Setup for Baseband Frequency Sweep and Undesired Sideband Nulling
The setup used to evaluate baseband frequency sweep and
undesired sideband nulling of the ADL5370 is shown in Figure 39. The interface board has circuitry that converts the single-ended I and Q inputs from the arbitrary function generator to differ-ential I and Q baseband signals with a dc bias of 500 mV.
Undesired sideband nulling was achieved through an iterative process of adjusting amplitude and phase on the Q channel. See Sideband Suppression Optimization in the Optimization section for a more detailed discussion on sideband nulling.
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OUTLINE DIMENSIONS
4.00BSC SQ0.60 MAX0.60 MAX1918EXPOSEDPAD241PIN 1INDICATOR*2.452.30 SQ2.156PIN 1INDICATORTOPVIEW3.75BSC SQ0.50BSC0.500.400.30(BOTTOMVIEW)131270.23 MIN2.50 REF1.000.850.8012° MAX0.80 MAX0.65 TYP0.05 MAX0.02 NOM0.20 REFCOPLANARITY0.08SEATINGPLANE0.300.230.18*COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2EXCEPT FOR EXPOSED PAD DIMENSION
Figure 40. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-2)
Dimensions shown in millimeters
ORDERING GUIDE
odel Temperature Range Package Description Package Option Ordering Quantity
1
ADL5370ACPZ-R2–40°C to +85°C 24-Lead LFCSP_VQ, 7” Tape and Reel CP-24-2 250 ADL5370ACPZ-R71–40°C to +85°C 24-Lead LFCSP_VQ, 7” Tape and Reel CP-24-2 1,500
1
ADL5370ACPZ-WP–40°C to +85°C 24-Lead LFCSP_VQ, Waffle Pack CP-24-2 64 ADL5370-EVALZ1 Evaluation Board
1
Z = Pb-free part.
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NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06117-0-10/06(0)
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