FM25L16_06资料

FM25L16 16Kb FRAM Serial 3V Memory Features 16K bit Ferroelectric Nonvolatile RAM • Organized as 2,048 x 8 bits • Unlimited Read/Write Cycles • 45 Year Data Retention • NoDelay™ Writes • Advanced High-Reliability Ferroelectric Process Very Fast Serial Peripheral Interface - SPI • Up to 18 MHz Frequency • Direct Hardware Replacement for EEPROM • SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Sophisticated Write Protection Scheme • Hardware Protection • Software Protection Low Power Consumption • Low Voltage Operation 2.7-3.6V • 1 µA Standby Current Industry Standard Configuration • Industrial Temperature -40°C to +85°C • “Green”/RoHS 8-pin SOIC Package • “Green”/RoHS 8-pin TDFN Package • TDFN Footprint Conforms to TSSOP-8 Description The FM25L16 is a 16-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 45 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. Pin Configuration CSSOWPVSS12348765VDDHOLDSCKSIUnlike serial EEPROMs, the FM25L16 performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after each byte has been transferred to the device. The next bus cycle may commence without the need for data polling. The product offers virtually unlimited write endurance, orders of magnitude more endurance than EEPROM. FRAM also exhibits much lower power during writes than EEPROM. /CS SO /WP VSS 1 2 3 4 Top View 8 7 6 5 VDD /HOLD SCK SI These capabilities make the FM25L16 ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. Pin Name Function /CS Chip Select /WP Write Protect /HOLD Hold SCK Serial Clock SI Serial Data Input SO Serial Data Output VDD Supply Voltage VSS Ground The FM25L16 provides substantial benefits to users of serial EEPROM as a hardware drop-in replacement. The FM25L16 uses the high-speed SPI bus, which enhances the high-speed write capability of FRAM technology. Device specifications are guaranteed over an industrial temperature range of -40°C to +85°C. This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s internal qualification testing and has reached production status. Rev. 3.0 Aug. 2006 Ordering Information FM25L16-G FM25L16-DG Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 www.ramtron.com Page 1 of 14 “Green”/RoHS 8-pin SOIC “Green”/RoHS 8-pin TDFN 元器件交易网www.cecb2b.com

WPCSHOLDSCKInstruction DecodeClock GeneratorControl LogicWrite ProtectFM25L16 512 x 32FRAM ArrayInstruction RegisterAddress Register CounterSI118Data I/O Register3Nonvolatile StatusRegisterSO Figure 1. Block Diagram Pin Descriptions Pin Name /CS Description Chip Select: This active low input activates the device. When high, the device enters low-power standby mode, ignores other inputs, and all outputs are tri-stated. When low, the device internally activates the SCK signal. A falling edge on /CS must occur prior to every op-code. SCK Input Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge. Since the device is static, the clock frequency may be any value between 0 and 18 MHz and may be interrupted at any time. /HOLD Input Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation for another task. When /HOLD is low, the current operation is suspended. The device ignores any transition on SCK or /CS. All transitions on /HOLD must occur while SCK is low. /WP Input Write Protect: This active low pin prevents write operations to the status register. This is critical since other write protection features are controlled through the status register. A complete explanation of write protection is provided on pages 6 and 7. SI Input Serial Input: All data is input to the device on this pin. The pin is sampled on the rising edge of SCK and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifications. * SI may be connected to SO for a single pin data interface. SO Output Serial Output: This is the data output pin. It is driven during a read and remains tri-stated at all other times including when /HOLD is low. Data transitions are driven on the falling edge of the serial clock. * SO may be connected to SI for a single pin data interface. VDD Supply Power Supply (2.7V to 3.6V) VSS Supply Ground I/O Input Rev. 3.0 Aug. 2006 Page 2 of 14 元器件交易网www.cecb2b.com

FM25L16 microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25L16 operates in SPI Mode 0 and 3. The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. A typical system configuration uses one or more FM25L16 devices with a microcontroller that has a dedicated SPI port, as Figure 2 illustrates. Note that the clock, data-in, and data-out pins are common among all devices. The Chip Select and Hold pins must be driven separately for each FM25L16 device. For a microcontroller that has no dedicated SPI bus, a general purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data pins (SI, SO) together and tie off (high) the Hold pin. Figure 3 shows a configuration that uses only three pins. Protocol Overview The SPI interface is a synchronous serial interface using clock and data pins. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25L16 will begin monitoring the clock and data lines. The relationship between the falling edge of /CS, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25L16 supports Modes 0 and 3. Figure 4 shows the required signal relationships for Modes 0 and 3. For both modes, data is clocked into the FM25L16 on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. The SPI protocol is controlled by op-codes. These op-codes specify the commands to the device. After /CS is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred. Note that the WREN and WRDI op-codes are commands with no subsequent data transfer. Important: The /CS must go inactive (high) after an operation is complete and before a new op-code can be issued. There is one valid op-code only per active chip select. Overview The FM25L16 is a serial FRAM memory. The memory array is logically organized as 2,048 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM25L16 and a serial EEPROM with the same pinout is the FRAM’s superior write performance. Memory Architecture When accessing the FM25L16, the user addresses 2,048 locations of 8 data bits each. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code, and a two-byte address. The upper 5 bits of the address range are ‘don’t care’ values. The complete address of 11-bits specifies each byte address uniquely. Most functions of the FM25L16 either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation is essentially zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. So, by the time a new bus transaction can be shifted into the device, a write operation will be complete. This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25L16 due to its fast write cycle and high endurance as compared with EEPROM. In addition there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that the FM25L16 contains no power management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that VDD is within datasheet tolerances to prevent incorrect operation. It is recommended that the part is not powered down with chip select active. Serial Peripheral Interface – SPI Bus The FM25L16 employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 18 MHz. This high-speed serial bus provides high performance serial communication to a host Rev. 3.0 Aug. 2006 Page 3 of 14 元器件交易网www.cecb2b.com

SCKMOSIMISOSOSPIMicrocontrollerSISCKSOSISCKFM25L16 FM25L16CSSS1SS2HOLD1HOLD2HOLDFM25L16CSHOLDMOSI : Master Out Slave InMISO : Master In Slave OutSS : Slave SelectFigure 2. System Configuration with SPI port P1.0P1.1 MicrocontrollerSOSISCKFM25L16CSP1.2HOLD Figure 3. System Configuration without SPI port SPI Mode 0: CPOL=0, CPHA=0 76543210 SPI Mode 3: CPOL=1, CPHA=1 76543210 Figure 4. SPI Modes 0 & 3 Rev. 3.0 Aug. 2006 Page 4 of 14 元器件交易网www.cecb2b.com

Data Transfer All data transfers to and from the FM25L16 occur in 8-bit groups. They are synchronized to the clock signal (SCK), and they transfer most significant bit (MSB) first. Serial inputs are registered on the rising edge of SCK. Outputs are driven from the falling edge of SCK. Command Structure There are six commands called op-codes that can be issued by the bus master to the FM25L16. They are listed in the table below. These op-codes control the functions performed by the memory. They can be divided into three categories. First, there are commands that have no subsequent operations. They perform a single function such as to enable a write operation. Second are commands followed by one byte, either in or out. They operate on the status register. The third group includes commands for memory transactions followed by an address and one or more bytes of data. FM25L16 WREN - Set Write Enable Latch The FM25L16 will power up with writes disabled. The WREN command must be issued prior to any write operation. Sending the WREN op-code will allow the user to issue subsequent op-codes for write operations. These include writing the status register and writing the memory. Sending the WREN op-code causes the internal Write Enable Latch to be set. A flag bit in the status register, called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted. Attempting to write the WEL bit in the status register has no effect. Completing any write operation will automatically clear the write-enable latch and prevent further writes without another WREN command. Figure 5 below illustrates the WREN command bus configuration. WRDI - Write Disable The WRDI command disables all write activity by clearing the Write Enable Latch. The user can verify that writes are disabled by reading the WEL bit in the status register and verifying that WEL=0. Figure 6 illustrates the WRDI command bus configuration. Table 1. Op-code Commands Name Description WREN Set Write Enable Latch Write Disable WRDI Read Status Register RDSR Write Status Register WRSR Read Memory Data READ WRITE Write Memory Data Op-code 0000 0110b 0000 0100b 0000 0101b 0000 0001b 0000 0011b 0000 0010b Figure 5. WREN Bus Configuration Figure 6. WRDI Bus Configuration Rev. 3.0 Aug. 2006 Page 5 of 14 元器件交易网www.cecb2b.com

RDSR - Read Status Register The RDSR command allows the bus master to verify the contents of the Status Register. Reading Status provides information about the current state of the write protection features. Following the RDSR op-code, the FM25L16 will return one byte with the contents of the Status Register. The Status Register is described in detail in a later section. WRSR – Write Status Register The WRSR command allows the user to select certain write protection features by writing a byte to the Status Register. Prior to issuing a WRSR command, the /WP pin must be high or inactive. Note that on the FM25L16, /WP only prevents writing to the Status Register, not the memory array. Prior to sending the WRSR command, the user must send a WREN command to enable writes. Note that executing a WRSR command is a write operation and therefore clears the Write Enable Latch. The bus configuration of RDSR and WRSR are shown below. FM25L16 Figure 7. RDSR Bus Configuration Figure 8. WRSR Bus Configuration features. They are nonvolatile (shaded yellow). The WEL flag indicates the state of the Write Enable The write protection features of the FM25L16 are Latch. Attempting to directly write the WEL bit in multi-tiered. First, a WREN op-code must be issued the status register has no effect on its state. This bit prior to any write operation. Assuming that writes are is internally set and cleared via the WREN and enabled using WREN, writes to memory are WRDI commands, respectively. controlled by the Status Register. As described above, writes to the status register are performed BP1 and BP0 are memory block write protection using the WRSR command and subject to the /WP bits. They specify portions of memory that are write pin. The Status Register is organized as follows. protected as shown in the following table. Table 2. Status Register Table 3. Block Memory Write Protection Bit 7 6 5 4 3 2 1 0 BP1 BP0 Protected Address Range Name WPEN 0 0 0 BP1 BP0 WEL 0 0 0 None 0 1 600h to 7FFh (upper ¼) Bits 0 and 4-6 are fixed at 0 and cannot be modified. 1 0 400h to 7FFh (upper ½) Note that bit 0 (Ready in EEPROMs) is unnecessary 1 1 000h to 7FFh (all) as the FRAM writes in real-time and is never busy. The WPEN, BP1 and BP0 control write protection Status Register & Write Protection Rev. 3.0 Aug. 2006 Page 6 of 14 元器件交易网www.cecb2b.com

FM25L16 This scheme provides a write protection mechanism, The BP1 and BP0 bits and the Write Enable Latch which can prevent software from writing the are the only mechanisms that protect the memory memory under any circumstances. This occurs if the from writes. The remaining write protection features BP1 and BP0 are set to 1, the WPEN bit is set to 1, protect inadvertent changes to the block protect bits. and /WP is set to 0. This occurs because the block protect bits prevent writing memory and the /WP The WPEN bit controls the effect of the hardware signal in hardware prevents altering the block /WP pin. When WPEN is low, the /WP pin is protect bits (if WPEN is high). Therefore in this ignored. When WPEN is high, the /WP pin controls condition, hardware must be involved in allowing a write access to the status register. Thus the Status write operation. The following table summarizes the Register is write protected if WPEN=1 and /WP=0. write protection conditions. Table 4. Write Protection WEL WPEN /WP Protected Blocks Unprotected Blocks Status Register 0 X X Protected Protected Protected 1 0 X Protected Unprotected Unprotected 1 1 0 Protected Unprotected Protected 1 1 1 Protected Unprotected Unprotected 8th clock). The rising edge of /CS terminates a Memory Operation WRITE op-code operation. The SPI interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the FRAM technology. Unlike SPI-bus Read Operation EEPROMs, the FM25L16 can perform sequential After the falling edge of /CS, the bus master can issue writes at bus speed. No page register is needed and a READ op-code. Following this instruction is a two-any number of sequential writes may be performed. byte address value. The upper 5-bits of the address are ignored. In total, the 11-bits specify the address of the first byte of the read operation. After the op-code Write Operation and address are complete, the SI line is ignored. The All writes to the memory array begin with a WREN bus master issues 8 clocks, with one bit read out for op-code. The next op-code is the WRITE instruction. each. Addresses are incremented internally as long as This op-code is followed by a two-byte address the bus master continues to issue clocks. If the last value. The upper 5-bits of the address are ignored. In address of 7FFh is reached, the counter will roll over total, the 11-bits specify the address of the first data to 000h. Data is read MSB first. The rising edge of byte of the write operation. Subsequent bytes are data /CS terminates a READ op-code operation. A read and they are written sequentially. Addresses are operation is shown in Figure 10. incremented internally as long as the bus master continues to issue clocks. If the last address of 7FFh is reached, the counter will roll over to 000h. Data is Hold written MSB first. A write operation is shown in The /HOLD pin can be used to interrupt a serial Figure 9. operation without aborting it. If the bus master pulls the /HOLD pin low while SCK is low, the current Unlike EEPROMs, any number of bytes can be operation will pause. Taking the /HOLD pin high written sequentially and each byte is written to while SCK is low will resume an operation. The memory immediately after it is clocked in (after the transitions of /HOLD must occur while SCK is low, but the SCK pin can toggle during a hold state. Rev. 3.0 Aug. 2006 Page 7 of 14 元器件交易网www.cecb2b.com

FM25L16 CSSC K SI SO 0 1 2 3 4 5 6 7 0 123456456701 2 3 Da t a 5 4 4 5 67op -c o d e 0 0 0 0 0 0 1 0 X XMS B 11-bit AddressXXX109321076 3 210LSBLSBMSB CS SCK 012345670Figure 9. Memory Write 1234564567012 345 67op-co de SISO0 0 000011X XMSB11-bit AddressXXX1093210LSBMSB76Da t a 5 4 32 1LSB0Figure 10. Memory Read Rev. 3.0 Aug. 2006 Page 8 of 14 元器件交易网www.cecb2b.com

FM25L16 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to VSS -1.0V to +5.0V VIN Voltage on any pin with respect to VSS -1.0V to +5.0V and VIN < VDD+1.0V TSTG Storage Temperature -55°C to + 125°C TLEAD Lead Temperature (Soldering, 10 seconds) 300° C VESD Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) 4kV 1kV - Charged Device Model (JEDEC Std JESD22-C101-A) Package Moisture Sensitivity Level MSL-1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply Voltage 2.7 3.3 3.6 V 1 IDD VDD Supply Current mA 0.3 0.15 @ SCK = 1.0 MHz mA 5.5 3.0 @ SCK = 18.0 MHz ISB Standby Current - 1 µA 2 ILI Input Leakage Current - ±1 3 µA ILO Output Leakage Current - 3 ±1 µA VIH Input High Voltage 0.7 VDD VDD + 0.5 V VIL Input Low Voltage -0.3 0.3 VDD V VOH Output High Voltage - V VDD – 0.8 @ IOH = -2 mA VOL Output Low Voltage - 0.4 V @ IOL = 2 mA VHYS Input Hysteresis (/CS and SCK only) 0.05 VDD - V 4 Notes 1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 2. SCK = SI = /CS=VDD. All inputs VSS or VDD. 3. VSS ≤ VIN ≤ VDD and VSS ≤ VOUT ≤ VDD. 4. Characterized but not 100% tested in production. Rev. 3.0 Aug. 2006 Page 9 of 14 元器件交易网www.cecb2b.com

AC Parameters (TA = -40° C to + 85° C, CL = 30pF) VDD 2.7 to 3.0V Symbol Parameter fCK SCK Clock Frequency tCH Clock High Time tCL Clock Low Time tCSU Chip Select Setup tCSH Chip Select Hold tOD Output Disable Time tODV Output Data Valid Time tOH Output Hold Time tD Deselect Time tR Data In Rise Time tF Data In Fall Time tSU Data Setup Time tH Data Hold Time tHS /Hold Setup Time tHH /Hold Hold Time tHZ /Hold Low to Hi-Z tLZ /Hold High to Data Active Notes FM25L16 VDD 3.0 to 3.6V Min Max Min Max Units Notes 0 15 0 18 MHz 30 25 ns 1 30 25 ns 1 10 10 ns 10 10 ns 20 20 ns 2 30 23 ns 0 0 ns 60 60 ns 50 50 ns 1,3 50 50 ns 1,3 5 5 ns 5 5 ns 10 10 ns 10 10 ns 20 20 ns 2 20 20 ns 2 1. tCH + tCL = 1/fCK. 2. Characterized but not 100% tested in production. 3. Rise and fall times measured between 10% and 90% of waveform. Power Cycle Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V) Symbol Parameter tPU Power Up (VDD min) to First Access (/CS low) tPD Last Access (/CS high) to Power Down (VDD min) tVR VDD Rise Time tVF VDD Fall Time Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.3V) Symbol Parameter CO Output Capacitance (SO) CI Input Capacitance Notes 1. This parameter is periodically sampled and not 100% tested. 2. Slope measured at any point on VDD waveform. Min Max Units Notes 1 - ms 0 - µs 50 - 1,2 µs/V 100 - 1,2 µs/V Min Max Units Notes - 8 pF 1 - 6 pF 1 AC Test Conditions Input Pulse Levels Input rise and fall times Input and output timing levels Output Load Capacitance 10% and 90% of VDD 5 ns 0.5 VDD 30 pF Rev. 3.0 Aug. 2006 Page 10 of 14 元器件交易网www.cecb2b.com

Serial Data Bus Timing FM25L16 /Hold Timing tHSCStHHSCKtHSHOLDtHH SOtHZtLZ Power Cycle Timing Data Retention (VDD = 2.7V to 3.6V, + 85° C) Parameter Min Max Units Notes Data Retention 45 - Years Rev. 3.0 Aug. 2006 Page 11 of 14 元器件交易网www.cecb2b.com

FM25L16 Mechanical Drawing 8-pin SOIC (JEDEC Standard MS-012, variation AA) Recommended PCB Footprint7.703.90 ±0.106.00 ±0.202.003.70Pin 11.270.654.90 ±0.101.351.750.250.5045°0.190.251.270.330.510.100.250.10 mm0°- 8°0.401.27 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. SOIC Package Marking Scheme Legend: XXXX= part number, P= package type LLLLLLL= lot code XXXXXXX-P RIC=Ramtron Int’l Corp, YY=year, WW=work week LLLLLLL RICYYWW Example: FM25L16, “Green” SOIC package, Year 2004, Work Week 38 FM25L16-G A40003G RIC0438 Rev. 3.0 Aug. 2006 Page 12 of 14 元器件交易网www.cecb2b.com

8-pin TDFN (3.0mm x 6.4mm body, 0.65mm pitch) FM25L16 6.40 ±0.1Exposed metal pad. Do not connect to anything, except Vss.Pin 1 IDPin 13.00 ±0.10.0 -0.050.75 ±0.050.20 REF.0.650.25 ±0.053.100.40 ±0.1Recommended PCB Footprint1.106.700.600.650.30Note: All dimensions in millimeters. This package is footprint compatible with the 8-pin TSSOP. TDFN Package Marking Scheme for Body Size 3mm x 6.4mm Legend: RIC=Ramtron Int’l Corp, G=”green” TDFN package RICG XXXX=base part number XXXX LLLL= lot code LLLL YY=year, WW=work week YYWW Example: “Green” TDFN package, FM25L16, Lot 0003, Year 2004, Work Week 38 RICG 5L16 0003 0438 Rev. 3.0 Aug. 2006 Page 13 of 14 元器件交易网www.cecb2b.com

FM25L16 Revision History Revision Date Summary 0.1 3/16/04 Initial Release 0.2 6/2/04 Replaced TSSOP with TDFN package. 1.0 10/22/04 Changed to Preliminary status. Added clarification to TDFN package drawing. Changed AC timing reference to 0.5 VDD. Added Power Cycling parameters and diagram. 2.0 3/10/05 Changed to Pre-Production status. Added ESD and package MSL ratings. Changed Data Retention spec. 2.1 7/18/05 Changed AC timings. Adjusted Idd values. 2.2 6/1/06 Removed IDD 100KHz and 5MHz entries. Improved IDD limits for 1MHz and 18MHz. 3.0 8/21/06 Changed to Production status. Changed tODV to 30ns (2.7 to 3.0V). Rev. 3.0 Aug. 2006 Page 14 of 14